Monday, December 21, 2009

The Tin Commandments - Just in Time for the Holidays!

The Tin Commandments
Copyright © DfR Solutions, College Park, MD, 2009 All Rights Reserved.

1. Thou shalt have no Lead (Pb) in the solder for EU (among other) applications.
The European Union, the USA, most industrialized Asian nations, etc., all require that all commercial products to be sold in their Countries must have hazardous materials (like Mercury and Lead) removed from PC Boards. The deadline for compliance was 2006 with elimination of some exemptions forthcoming. The most common Pb-free solder alloys consist mostly of tin with small additions of silver an copper. Some question why the electronics industry, which accounts for less than 0.1% of the lead in land-fills, was targeted by the EU. It matters not, since the train has now left the station. Even exempt industries such as telecommunications, medical, and the military are finding it increasingly difficult to continue using Pb.

2. Thou shalt not make Tin (Sn) whiskers that will cause short circuits.
Pure Tin tends to make “whiskers”, a short growth from the main body of Tin, and small Tin lands make the whiskers grow the most. Historically 1-2% Lead (Pb) was used to prevent whiskering in tin coatings. Various methods are used to mitigate whisker growth without use of Pb but the only way to prevent it is use coatings such as Pd or Au.

3. Thou shalt not take Pb-free ball grid array components and solder them onto a Pb-based solder pad.
Though it is not impossible to achieve a reliable mixed solder joint, the component must reach 230°C to do so. The PCB and other components must be designed to survive the higher temperature.

4. Remember the Sabbath Day (and 2nd and 3rd shift workers).
Building high quality products with Pb-free solder requires consistently hitting a much more narrow process window. Your off hour workers must be trained just as well as the 1st shift workers.

5. Honor thy supplier qualification and process control requirements.
In order to ensure that you get the materials you specify, trust the documentation from your suppliers.

6. Thou shalt not kill your boards with the higher temperatures in reflow ovens in a Lead-free application.
Notice that the temperature difference in most SMT re-flow ovens between a Leaded Solder and a Lead-free Solder is about 35 degrees C. Specifying the appropriate board properties is critical to prevent delamination, warping, cracked vias, or worse. Components must also be specified to survive reflow conditions (JST-020C should be followed religiously).

7. Thou shalt not mate female Gold connectors with male Tin connectors (or vice versa).
The reason for this is because of the inter-metallic that is made between Gold and Tin (or a solder Tin alloy) when they are repeatedly rubbed together. Build up of this inter-metallic can cause an open connection. If you need a good connection, use gold with gold. Tin with tin is also acceptable for applications where fretting is not a concern.

8. Thou shalt not steal published quality and reliability data.
Since your environment is unique to you, don’t expect to get similar results when you application differs from that of published reports.

9. Thou shalt not bear with the same rework standards after going Lead-free.
Experience shows that the re-work stations in most PC Board manufacturing facilities are often overlooked as an essential area that must be controlled. Hitting the small process window requires well controlled rework profiles and often new equipment. “Touch up” areas are becoming extinct because of the extra heat of the solder iron that’s required in a Lead-free process. The quality of all rework processes should be validated with close inspection.

10. Thou shalt not covet the Tin mines in China, Indonesia, and South America.
It’s true that our planet’s main resources for Tin are in China (40%), Indonesia (20%) and South America (20%) and yet it seems that Chinese companies are buying up another Tin mine every week. Tin is available in mines across our world, but the best mines are not in the Americas or Europe.


Copyright 2009 by DfR Solutions and VALUE Engrafting. All Rights Reserved.

Thursday, November 12, 2009

Quality & Regulatory Environment in Medical Device Industry

I attended this ASQ presentation in Austin on Thursday, November 11th. I found the presentation very informative and quite illuminating. Some highlights are outlined in the next few bullets.

Description of Event:Speaker: Evangeline Loh, Ph.D., RAC (US, EU), Emergo Group

The medical device industry is estimated to be a $210 billon dollar industry, (1).  The definition of a medical device varies slightly around the world. The US is the largest market in both consumption and production (40% total market consumption). Japan is the next largest, and then Germany. This presentation will provide a brief overview of the global regulations for medical devices. In particular, the following countries/markets will be included: US, EU, Japan, Australia, China, and Canada. The quality system required for manufacturers will be discussed as well as medical device definitions and classifications. Harmonization has become a recent objective of the medical device industry and information on these endeavors will be provided.
(1) Acmite Market Intelligence, Study: World Medical Device Market

Key Takeaways:

Surprisingly, there is not a good, uniform definition of what exactly a medical device is. There is also an increasing overlap in technologies combining medical devices with biologics or drugs. Example: Stent coated with antibiotics. How the device is regulated depends upon the primary function of the product. In the example above, since the stent is performing the primary function of holding a blood vessel open, it is regulated in the US a a medical device. If the primary function was to deliver medication, it would be regulated as a drug. This is becoming an extremely complex area of regulation.

Worldwide, the two most commonly accepted medical device standards are ISO 13485 (EU) – Medical Devices, Quality Management Systems and FDA 21 CFR Part 820 (US) – Good Manufacturing Practices for Medical Devices. The ISO standard is the most widely accepted worldwide but is not currently recognized by the US. The two standards are ~ 95% equivalent.

There is a Global Harmonization Task Force (GHTF) currently issuing guidelines for a common worldwide structure for regulating medical devices.

Worldwide, there are two basic regulatory schemes for medical devices.

US Model:
Basic classes of devices identified
Specific letter codes to identify products very specifically
May hinder innovation since new/novel products require a longer process to have a letter code created for the device in addition to the other regulatory devices
Quality management system and registration required
Good Management Practices (GMR)
Ongoing compliance mandatory, FDA 21 CFR Part 820
Frequency of audits based on classification
CAPA feedback
Design controls

EU Model
CE marking is the ultimate goal
De facto expectation to annually certify to ISO 13845
Basic classes of devices identified
Broad letter codes that are more functional than specific in nature, generic rules not prescribed categories
Thought to allow more rapid approval of new/novel devices
Risk management required
Essential requirements identified
Labeling + Language requirements
Technical files
Design Controls
Clinical evaluation
Traditionally easier/faster to get certified in Europe than in the US

In the US, there are three broad classes of medical devices – Class I, Class II, and Class III. A class I device example is a toothbrush. Class II – stent, infusion pump. Class III – implantable heart pump

Compliance to the FDA standard is managed by:
Device submission material
FDA audits/inspections
Form 483 / warning letters
Adverse Event reporting system
Typical new approval process takes 1 year or more but is considered relatively efficient by worldwide standards.

Even the highest risk Class III device manufacturers only get audited by the FDA once every 2 years on average. The FDA can issue warning letters or non-compliance letters based on severity of issues found.

Device changes require FDA notification. There is an FDA flowchart detailing change requirements based on device type and significance of change made.
Reliability is never explicitly mentioned.

Design requirements are as follows:
Design Input, Design Output, Design review, Design verification, Design validation, design transfer, design changes, design history file. No specific testing recommendations or requirements are identified (types of tests, # of units tested, success rates, etc.).

Quality is handled via the Quality Management System requirements. Again. there are no hard and fast rules only general guidelines.

Statistics / sampling plans / CAPA feedback are required but no goals or requirements or set. The system seems to encourage setting a low bar on quality since the audits are keyed on attaining goals that were set.

Although there is some recognition of risk versus reward in the US, Europe gives greater consideration to this aspect. Example: All medical devices pose an inherent risk to the patient. Even relatively simple ones like catheters can cause death due to blood stream infection. For more complex cases like heart pumps, the device risk may be higher but the patient’s risk of non action is also higher. This is giver greater consideration in Europe than in the US.

Interestingly, ISO 13485 does not seem to require continuous improvement like ISO 9001. It does require implementation and maintenance of a quality management system.
The end result is a product CE marking followed by 4 digits with identify the notified body.

Classes I, II, and II with codes MDD (medical), VDD (in vitro), and AIMDD (active implantable, implantable)

EU makes a distinction between “cosmetic” and “medical” devices. Toothbrushes, wrinkle creams, etc are considered cosmetic and not regulated in the same manner.

ISO 13485 is specific to medical devices. It contains the elements of ISO 9001 plus:
Cleanliness requirements
Risk management
Post market surveillance requirements
Implantable requirements

Monday, November 2, 2009

Visit to Bay Area

Just came back from the Bay Area. Fascinating visit to a broad spectrum of companies, including consumer electronics, medical, telecom, and component manufacturers.

I was truly impressed by almost every companies' increasing focus on reliability assurance, especially in regards to the movement away from 'no-thinking' MTBF and FMEA activities and a much greater interest in developing a 'Best in Class' process, including DFMEA with risk-reduction actions that can be tracked and monitored through SPC, DfX principles, design verification in combination with root-cause analysis, and product qualification plans based on physics of failure.

With a tight economy and decreasing margins, executive management is increasingly realizing that attacking product performance earlier in the process and farther down the supply chain reduces product development costs, accelerates time to market, and reduces those "Oh-Oh's" that can ruin a career.

I am going to LA on Friday. Let's see if the same mentality that exists up in NoCal is alive and well in SoCal

Tuesday, October 27, 2009

Recap of the Austin CTEA Expo & Tech Forum

There was a fantastic turnout at the Austin CTEA Expo & Tech Forum last Thursday, October 22nd! CTEA put together a great program and a great vendor show. The four technical presentations were well-attended, averaging over 60 people per session, and drew many questions, comments, and feedback. The presentations were:

"Manufacturing and Reliability Challenges With QFN" Cheryl Tulkoff, DfR Solutions

"Troubleshooting SMT Yield Problems In a Lead Free World" Ray Prasad, Ray Prasad Consultancy Group

"New and Emerging Technologies in Electronics" Daniel F. Baldwin, Ph.D., Engent, Inc.

"Intellectual Property Law" Kim-Marie Vo, Freescale Semiconductor

To see the presentations made last week, click here.

CTEA (Central Texas Electronics Association) is a combination of the SMTA and IMAPS, organized to foster knowledge sharing and networking across the fields of electronics design, IC assembly, PCB assembly, and related technology arenas in the central Texas region.

Wednesday, October 14, 2009

DfR to present at Austin CTEA Expo & Tech Forum Next Week

On Thursday, October 22nd, Cheryl Tulkoff will present,"Manufacturing and Reliability Challenges With QFN" at the Austin CTEA Expo & Tech Forum.

CTEA (SMTA/IMAPS) Austin Expo & Tech Forum
Thursday, October 22, 2009 - Next Thursday!
Norris Conference Center, Austin, TX


Join the Central Texas Electronics Association(CTEA) for their popular annual event, featuring exhibiting companies, networking opportunities, technical presentations including a keynote address given by Dan Baldwin, current SMTA president, free lunch, great doorprizes... and more!

Pre-register online now at: http://www.smta.org/education/vendor_days/vendor_days.cfm#austin

When: Thursday, October 22, 2009
Where: Norris Conference Center, 2525 W Anderson Ln # 365, Austin, TX 78757
Show Hours: 10:30am-5pm
Free Lunch: 12pm

Technical Program:

11:10AM "Manufacturing and Reliability Challenges With QFN"
Cheryl Tulkoff, DfR Solutions

1:20PM "Intellectual Property Law: What Non-Attorneys Should Know"
Kim-Marie Vo, JD, Freescale Semiconductor

2:40PM "Troubleshooting SMT Yield Problems in a Tin-Lead and Lead Free World"
Ray Prasad, Ray Prasad Consultancy Group

3:40PM KEYNOTE PRESENTATION
"New and Emerging Technologies in Electronics"
Dan Baldwin, Ph.D., CEO, Engent, Inc. & current SMTA President

To view an EXHIBITOR LISTING and additional information on the technical program, please visit:

http://www.smta.org/education/vendor_days/vendor_days.cfm#austin

We’ll see you on October 22nd!

Wednesday, October 7, 2009

Design for Excellence Course (DfX), Oct 19-22

DfR Solutions, in collaboration with A.T.E. Solutions and IPC, will hold the first ever Design for Excellence (DfX) Course, October 19-22. This collaborative effort will provide tools on how to meet time-to-market deadlines and reduce warranty issues. For more information, please click here.

Tuesday, October 6, 2009

Root-Cause Analysis in the HALT Process - Webinar Now Available!

Dr. Craig Hillman's Webinar presentation "Root-Cause Analysis in the HALT Process" part of the series Ask the Experts hosted by the Qualmark Corporation, is now available on our website! To access the presentation, please click here.

Wednesday, September 30, 2009

IEEE ASTR Workshop October 7-9. Now Available via WEBINAR!

Below is the most up-to-date information for this year’s ASTR Conference on October 7-9 in Jersey City, New Jersey. We have locked in the schedule of speakers and have a great line-up this year, including a panel discussion on the Green/Clean Tech Industry and the role that Accelerated Testing will be playing in this industry.

The big news is now we are offering the conference via webinar as on option. So if you were not able to make it before due to travel restrictions at your company or because you couldn’t get away from the office for a few days, now you can still attend the conference from your desk. And we are offering the conference at half price for this option. Three full days of technical information delivered to your desktop for only $350 (IEEE members) or $375 (non-IEEE members).

CONFERENCE DATES: October 7-9, 2009

Workshop Website


Theme this workshop: RENEWABLE RELIABILITY

Schedule of Events

Over the last few years, Accelerated Stress Testing & Reliability (ASTR) has been embraced by an ever widening array of worldwide companies seeking to reconcile the need for the highest quality product with the necessary push for early time-to-market. The purpose of the ASTR Workshop is to share ideas on better ways of accelerating and detecting hidden defects, flaws, and weaknesses in electronic and electro-mechanical hardware that would result in failures during usage. These techniques are focused on testing electronic hardware to operation and destruction limits and root cause investigation to determine the physics-of-failure. The goal of AST is to produce mature products at market introduction and efficient an effective sampling screens to monitor for manufacturing excursions with high combined stresses (beyond end-use specifications) for shorter lengths of time. The 2009 workshop will focus on ASTR topics in renewable reliability. This theme will be timely, considering emerging world wide investments towards development and commercialization of sustainable and green energy technologies to generate economic growth and environmental security. The workshop will be held at the Hyatt Regency Jersey City on Hudson, overlooking the New York City skyline.

- Cheryl Tulkoff, ASTR 2009 Chair


CONFERENCE INFO

Date: October 7-9, 2009

Location: Jersey City, NJ (Hyatt Regency Jersey City)

Hyatt's Website

Go Directly to the Online Registration Page

Tuesday, September 29, 2009

Dr. Randy Schueller to present at SMTAI San Diego, Oct. 4-8

Dr. Randy Schueller of DfR Solutions will be very busy out at SMTAI San Diego next week! Randy is giving a class on Reliability of Green Electronics, presenting the two papers, and chairing a session on PCB surface finishes.

Check back after the event for a recap! Some details on the sessions and what he'll be up to:

The Reliability of ‘Green’: Going Beyond SAC305- Sunday, October 4
Randy Schueller, Ph.D., DfR Solutions

What You Will Learn
As the RoHS legislation enters its third year, knowledge of the basics of Pb-free design and manufacturing is proliferating. Consumer electronic OEMs have been manufacturing Pb-free electronics for several years while even companies that produce higher reliability products (telecom, industrial, medical, military, avionics) have made the transition or are in the process of preparing for the eventual demise of SnPb. Unfortunately, the introduction of new environmental legislation and new environmental-friendly materials continues at a rapid pace. As a result, the design / manufacturing / component / reliability engineer continues to struggle with new Pb-free alloys and halogen-free materials, among other issues. While this course will provide a comprehensive overview of some of the challenges of Pb-free, it will also focus on some of the newest issues in ‘green’ electronics. These will include tin whisker mitigations, halogen-free laminate, manufacturing challenges that continue to be a problem with Pb-free, the performance of second (2nd) generation Pb-free solders, and the newest long-term reliability information for Pb-free.

Who Should Attend
This course is geared toward engineers and managers in the areas of product development, manufacturing, quality, or reliability. Nearly all companies are migrating toward green products whether or not it is intentional. As non-green materials in the electronics industry are phased out, it is critical to understand the key differences and reliability issues that can result from the new material and processes. Consequently, anyone involved in the early life cycle of a product who wishes to mitigate the risk of failure would find value in attending this course.

Topics Covered
  • Components
    • Understanding process sensitivity levels (PSL)
    • Tin Whisker: predictions and mitigations
  • Printed Circuit Boards
    • Predicting and preventing printed board damage
    • Newest Pb-free solderability finishes
    • Halogen-free laminates: the good, the bad, and the ugly
  • Solder and Manufacturing
    • 2nd generation solders: what/who/why
    • Finding a solution to hole fill
    • Is Pb-free the culprit to head-in-pillow?
  • Long-Term Reliability
    • Temperature cycling
    • Mechanical shock
    • Vibration
Alternate Lead-Free Alloys - Tuesday, October 6
The advent of lead-free soldering with the de-facto SAC305 standard and its close relatives has resulted in poor performance and increased cost in some applications. It is only natural that research for substitute materials would transpire. This session will cover some of the work in this arena, most notably Investigations on the processability of SnCuNi alloy for SMT assembly, efforts to minimize and standardize the number of lead-free alloys used, and experimental data and its interpretation for some "second generation" lead-free alloys. The papers will present process development, reliability data, and explanation of the results. This session is ideal for the person who wants to be brought up to speed on what is happening in alternative lead-free alloys to improve performance and reduce cost.

  • Second Generation Lead-Free Alloys
    Randy SchuellerSpeaker of Distinction, Ph. D., Nathan Blattau, Ph.D., Joelle Arnold, and Craig Hillman, Ph.D., DfR Solutions

  • Options for Controlling Moisture Sensitivity in Packages and PWBs During Assembly- Tuesday, October 6
  • Pb-Free Reflow, PCB Degradation, and the Influence of Moisture Absorption
    Randy SchuellerSpeaker of Distinction, DfR Solutions

  • New Technical Advancements in PCB Surface Finishes - Wednesday, October 7
    Chair: Randy Schueller, Ph.D., DfR Solutions

    The surface finish one selects for the PCB is oftentimes the most critical decision in enabling a successful assembly process, and ultimately a reliable end product. The fact that there are half a dozen widely used surface finishes currently on the market suggests there is no single one that meets the many needs of the industry and thus sacrifices are being made. Much research and development is taking place to significantly improve existing surface finishes and in some cases invent new finishes with attributes suitable for a wider range of products. This session contains three excellent papers; the first addresses the important issue of controlling creep corrosion failure on immersion silver PCBs. The new use of organic metals to greatly improve the characteristics of immersion tin finishes is presented in the second paper. The final paper is the revealing of a promising new surface finish material with many attractive properties for the electronics industry. Anyone involved in design, assembly, or reliability would benefit from this session.


    Monday, September 28, 2009

    Dr. Nathan Blattau to present Oct 8th at the IEEE ASTR Workshop in Jersey City, NJ

    On Thursday, October 8th, Dr. Nathan Blattau will present, "Thermo-mechanical Fatigue Testing of Printed Circuit Card Assemblies Using Power Cycling" at the annual IEEE ASTR (Accelerated Stress Testing and Reliability) Workshop in Jersey City, NJ.

    Check back after the event for a recap and link to his material and presentation!

    About the ASTR Workshop
    Over the last few years, Accelerated Stress Testing & Reliability (ASTR) has been embraced by an ever widening array of worldwide companies seeking to reconcile the need for the highest quality product with the necessary push for early time-to-market. The purpose of the ASTR Workshop is to share ideas on better ways of accelerating and detecting hidden defects, flaws, and weaknesses in electronic and electro-mechanical hardware that would result in failures during usage. These techniques are focused on testing electronic hardware to operation and and destruction limits and root cause investigation to determine the physics-of-failure. The goal of AST is to produce mature products at market introduction and efficient an effective sampling screens to monitor for manufacturing excursions with high combined stresses (beyond end-use specifications) for shorter lengths of time. The 2009 workshop will focus on ASTR topics in renewable reliability. This theme will be timely, considering emerging world wide investments towards development and commercialization of sustainable and green energy technologies to generate economic growth and environmental security. The workshop will be held at the Hyatt Regency Jersey City on Hudson, overlooking the New York City skyline.

    Saturday, September 26, 2009

    IPC Midwest - PCB Session Summary

    At IPC Midwest last week, I presented "Pb-Free Reflow, PCB Degradation, &
    the Influence of Moisture Absorption
    " in the Challenges in Building a High Reliability Military PWB session. The session was attended by approximately 21 folks interested in the latest information on PCBs. They had a lot of great questions and feedback for us.

    Later, I was interviewed about the paper by iconnect007. Complete audio/video interviews of all the PCB presentations can be viewed online.

    Session details:

    Reliability in mission-critical systems is a matter of life and death. This first of two sessions on reliability, will dissect the critical components of reliability for the printed board. If you are concerned about board reliability in the harsher manufacturing environments of lead free, this session is for you.

    The Impact of Converting Flex Circuits from HASL to a RoHS Compliant Surface Finishes

    • Al Wasserzug, Vulcan Flex Circuit Corporation
    Design Considerations for High Reliability PCB

    • Rajesh Kumar, Dynamic Details, Inc.
    Pb-Free Reflow, PCB Degradation, and the Influence of Moisture Absorption

    • Cheryl Tulkoff, DfR Solutions
    Later, I moderated the Printed Board Reliability Issues session. Equally well-attended by an enthusiastic audience, it continued the discussion from the earlier PCB session.

    In the second session on board reliability, we expand on the issues for via reliability and the transition of telecom products into the era of lead free. Join us for the latest information.

    Microvia Reliability Failure Modes

    • Paul Reid, PWB Interconnect Solutions Inc.
    Bare Board Material Performance after Pb-free Reflow

    • Ted Lach, Alcatel-Lucent
    Water Vapor Uptake And Release In Printed Boards

    • Joseph Kane, BAE Systems Platform Solutions

    Sunday, September 20, 2009

    Manufacturing & Reliability Challenges with QFN: CTEA on Oct 23rd

    One of the fastest growing package types in the electronics industry today is the quad flat pack no lead (QFN), also known as a bottom-termination SMT component. While the advantages of QFNs are well documented, concerns arise with manufacturability, compatibility with other OEM processes, and reliability.

    I've published two articles on this topic. Part I addresses the manufacturing aspects while Part II addresses the reliability aspects.

    I'll be presenting on QFN challenges next at the:

    Central Texas Electronics Association (SMTA/IMAPS) Expo & Tech Forum

    in Austin, TX on Thursday, October 23rd.

    Registration to attend the event is free!

    Friday, September 18, 2009

    DfR Solutions to present at IEEE ASTR 2009

    Dr. Nathan Blattau, Vice President and Chief Scientist at DfR Solutions, will present "Thermo-mechanical Fatigue Testing of Printed Circuit Card Assemblies Using Power Cycling" at the annual IEEE ASTR (Accelerated Stress Testing and Reliability) 2009 Workshop in Jersey City, NJ on Thursday, October 8th.

    Check out the workshop at:

    http://www.ewh.ieee.org/soc/cpmt/tc7/ast2009/

    Check back here after the event for a recap and complete presentation details.

    IEEE ASTR Workshop: October 7-9, 2009

    Over the last few years, Accelerated Stress Testing & Reliability (ASTR) has been embraced by an ever widening array of worldwide companies seeking to reconcile the need for the highest quality product with the necessary push for early time-to-market. The purpose of the ASTR Workshop is to share ideas on better ways of accelerating and detecting hidden defects, flaws, and weaknesses in electronic and electro-mechanical hardware that would result in failures during usage. These techniques are focused on testing electronic hardware to operation and and destruction limits and root cause investigation to determine the physics-of-failure. The goal of AST is to produce mature products at market introduction and efficient an effective sampling screens to monitor for manufacturing excursions with high combined stresses (beyond end-use specifications) for shorter lengths of time. The 2009 workshop will focus on ASTR topics in renewable reliability. This theme will be timely, considering emerging world wide investments towards development and commercialization of sustainable and green energy technologies to generate economic growth and environmental security. The workshop will be held at the Hyatt Regency Jersey City on Hudson, overlooking the New York City skyline.

    http://www.ewh.ieee.org/soc/cpmt/tc7/ast2009/

    Surface finishes for lead free processing

    Does anyone have quick reference guide or resource for advantages and disadvantages for various surface finishes in lead free processing including surface mount, wave, selective and hand soldering.

    Tuesday, September 15, 2009

    Visiting AssemblyTech Show

    Bob and I will be in Chicago next week learning about some new advances in selective soldering at Pillarhouse USA, during our trip we will stop by the AssemblyTech show on Wednesday morning September 23.

    DfR Solutions at IPC Midwest, Sept. 23-24, 2009

    I'll be attending IPC Midwest in Schaumburg, Illinois next week where I'll moderate a panel, present a paper, and be interviewed by iconnect007.

    While there,I will present "Pb-Free Reflow, PCB Degradation, and the Influence of Moisture Absorption" in the session:

    S03 Challenges in Building a High Reliability Military PWB
    Wednesday, 9/23/200910:00 AM - 12:00 PM



    I'll moderate this session:

    S06 Printed Board Reliability Issues
    Wednesday, 9/23/20091:30 PM - 3:00 PM



    Finally, I'll have an interview about the PCB paper with Ray Rasmussen and Steve Gold at the show floor studio at Booth 507 at 11 on Thursday, 9/24/09.

    If you'll be at IPC Midwest, please look me up! Otherwise, check back here after the event and I'll have all the material and event recap posted.

    For further information, check out these links:

    www.ipcmidwestshow.org/html/main/default.htm

    www.iconnect007.com/pages/iconnect007.cgi

    Tuesday, August 11, 2009

    DfR Solutions, in association with Louis Ungar of A.T.E. Solutions and with contributions from IPC, will hold a four day professional development course titled "Design for Excellence" (DfX), October 19-22, 2009 in College Park, Maryland.

    This one-of-a-kind collaborative effort will provide designers, reliability personnel, and engineering management with tools on how to meet time-to-market deadlines and reduce warranty issues.

    Areas to be covered include Design for Reliability, Design for Manufacturability, Design for Testability, and Design for Environment. Attendees will be eligible to earn Professional Development Hours (PDH) or Continuing Education Units (CEU).

    For additional information, including course outlines, please click here.

    Tuesday, July 21, 2009

    About DfR

    About DfR

    Our History

    DfR Solutions was initially formed by several senior scientists and staffers from the University of Maryland’s Center for Advanced Life Cycle Engineering (CALCE) for Electronic Product and Systems, and has grown to include personnel with backgrounds from several industries (automotive, avionics, contract manufacturing, industrial controls, and superconductors). To learn more about our personnel, please visit our DfR Staff.

    We’re Here to Help You

    The staff at DfR Solutions has world-renowned expertise in applying the science of Reliability Physics to electrical and electronics technologies, and the company is a leading provider of quality, reliability, and durability (QRD) research and consulting for the electronics industry. DfR’s integrated use of PoF Reliability Prediction (PoF) and Best Practices provides crucial insights and solutions early in product design and development, and throughout the product life cycle.

    The personnel at DfR are motivated to provide companies maximum value in their reliability activities and to promote openness and exchange of information. After performing over 250 root-cause investigations over the past four years, the scientists and engineers at DfR have made a name for themselves as world leaders in failure analysis and accelerated testing of electronics.

    We also excel through our strong partnerships with the leading companies in the field of electronics and software, which include Qualmark (HALT), Engent (advanced SMT assembly) and Ops A La Carte (reliability capability assessment). By providing a turnkey solution to all issues in electronics, from component specifications to lifetime predictions, from connector plating to IGBT functionality, DfR Solutions will take your reliability concerns — and make them ours.

    Open Door Policy

    DfR Solutions has an “open door” policy. We welcome your questions or concerns. Please call us at 301-474-0607 or email us for a complimentary consultation regarding your needs.