Thursday, March 29, 2012

AHOT IPC Designers Council Meeting on Tues. April 10th

Austin Heart of Texas IPC Designers Council April General Meeting

Tuesday, April 10, 2012
6:00 P.M.

AHOT Meeting Information—Impedance Design Considerations

Our presenter, David Gorden, is Senior Field Applications Engineer at DDI Global.

Presentation will include the following subtopics:

  • Trace width and material impact
  • Impedance configurations
  • Stack-up considerations

Pizza and drinks will be provided. Please RSVP to Linda at 512-259-2465, or email

Location: Cadence Design Systems, Inc.
12515-7 Research Boulevard, Ste 250
Austin, Texas 78759


Wednesday, March 28, 2012

CTEA Electronics Design & Manufacturing Symposium

Central Texas Electronics Association (Joint Chapter of IMAPS & SMTA Members) Presents:

Electronics Design & Manufacturing Symposium

Tuesday, April 17, 2012

Virtex Assembly at 12234 N. I-35 & W. Yager Lane, Bldg A


2:00 - Registration Begins

2:30 - Welcome and Virtex Assembly Factory Overview

2:35 - Virtex Assembly Factory Tours

3:35 - "Conflict Minerals Legislation and its impact on Electronic Manufacturing”

Brad Heath, President, Virtex Assembly

4:05 - "Evolving Counterfeit Component Threats and Industry Mitigation Efforts"

Stephen Schoppe, President, Process Sciences Inc (PSI)

4:35 - Break & Networking

4:50 - "Factors for a Green Cleaning Process”

Ram Wissel, Technology Manager, Kyzen

5:20 - "Green Trends and Innovations in the Electronics Industry"

Albert Tsang, Environmental Affairs, Dell

5:50 - Closing Remarks

6:00 - Food & Refreshments Served and More Networking


RSVP to Bob Baker at:

There is no charge for SMTA and IMAPS members; $10 for all non-members

Event Location:

Virtex Assembly at 12234 North I-35 & W. Yager Lane, Bldg A, Austin, Texas

See Map at: (Map to Virtex)

Save the Date: Another CTEA Symposium is scheduled for 6/13 at Cerium Labs

Friday, March 23, 2012

SMTA Webtorial on Pad Cratering on April 12 & 19

Cheryl Tulkoff will be presenting "Pad Cratering and Pb-Free" during these webinars. For more information or to register, please visit the SMTA website.

SMTA Webtorial: Pad Cratering

Two (2) 90 minute Sessions
Thursday, April 12 and 19, 2012
1:00pm to 2:30pm Eastern
Presented by: Cheryl Tulkoff, DfR Solutions

What You Will Learn:
Pad cratering is defined as cracking which initiates within the laminate during a dynamic mechanical event such as In Circuit Testing (ICT), board depanelization, connector insertion, and other shock and vibration inducing activities. During this webtorial, you'll learn the key drivers, measurement and detection protocols, and preventive tactics for this serious but prevalent failure. Pad cratering was first recognized in BGA packages but newer leadless, bottom termination components are also vulnerable.

Topics Covered:
  • Pad Cratering Defined
  • Is Pad Cratering a Pb-free issue?
  • At risk components
  • Drivers
  • Finer pitch components
  • More brittle laminates
  • Stiffer solders (SAC vs. SnPb)
  • Presence of a large heat sink
  • Detection and Failure Analysis Procedures: Which ones are effective & why
  • X-ray
  • Dye-n-pry
  • Ball shear
  • Ball pull
  • Mitigation Practices & Solutions to Pad Cratering
  • Board Redesign
  • Solder mask defined vs. non-solder mask defined
  • Limitations on board flexure
  • 750 to 500 microstrain, Component dependent
  • Specification and Procedure Discussion
  • Strain Gage Testing Protocols
  • ICT Fixture Evaluation
  • Assembly Process Evaluation
  • Process Specifications
  • More compliant solder
  • SAC305 is relatively rigid, SAC105 and SNC are possible alternatives
  • New acceptance criteria for laminate materials
  • Intel-led industry effort
  • Attempting to characterize laminate material using high-speed ball pull and shear testing, Results inconclusive to-date
  • Alternative approaches
  • Targeted Audience:
    Design, Manufacturing, and Failure Analysis Engineering

    Instructor Bio:
    Cheryl Tulkoff is an industry renowned expert in the fields of semiconductor fabrication, electronics assembly, RoHS conversion, and reliability engineering and management. Prior to joining DfR, Ms. Tulkoff had an active leadership role both within her employer's companies and among regional and national electronics and reliability organizations. At her most recent position at National Instruments, Cheryl developed a comprehensive reliability organization, including the creation of an internal failure analysis group and a closed loop reliability program. She has also taken the lead in process development and implementation in semiconductor fabrication through her work at Cypress Semiconductor in electronics assembly, and through her work at IBM. Cheryl is the head of DfR's office located in Austin, Texas, which opened in February 2009. B.S., Mechanical Engineering (Georgia Institute of Technology)

    Thursday, March 22, 2012

    Wednesday, March 21, 2012

    Do You Have The Knack?

    Have you ever felt a strong need to repair your neighbor's washing machine? Or add Wi-Fi to your toaster? Do you have nine computers in various states of assembly on your living room floor? If the answer is yes to any of these questions, you just might have the KNACK. While not curable, the KNACK could lead to a rewarding career in engineering. Just ask our most recent hire, electrical/mechanical/software engineering guru, Justin Wilkins.

    Tuesday, March 20, 2012

    Physics of Failure

    How important is Physics of Failure (PoF)? Important enough for over eight hundred (8-0-0!) people to view Jim McLeish's recent joint webinar with the American Society of Quality (ASQ) on PoF Reliability Methods. If you missed the opportunity to learn about this ground-breaking approach to design assurance, you can still download the entire presentation. For more information, contact Jim McLeish.

    Monday, March 19, 2012

    How Hot is Too Hot?

    While thermal analysis tools have improved their ability to predict component temperatures, they have failed to answer the most important question: How Hot is Too Hot? In this informative article (warning: ad before article), DfR Solutions explains how classic derating is insufficient and true understanding of component degradation is necessary to optimize product design and performance. For more information, contact Greg Caswell.

    Friday, March 16, 2012

    DfR Solutions' Sherlock Helps Eliminate Pad Cratering

    Tired of breaking components during Bed of Nails In-Circuit Testing (ICT)? DfR's Automated Design Analysis Tool, Sherlock, now provides an elegant solution to this consistent design for manufacturability (DfM) problem. Within a matter of minutes, test points, components, and supports can be arranged and located to minimize board flexure and effectively eliminate pad cratering or solder joint cracking. For more information, contact Tom O'Connor.