Increased circuit board densities coupled with the need for higher electrical performance have resulted in a new reliability challenge, that of vias in close proximity to either SMT or BGA pads. In an effort to reduce inductance, increase density or employ finer pitch array packages, via pads are being placed close to the SMT/BGA lands. Thicker PWBs, due to higher I/O array packages exacerbate these issues as larger holes and pads may be required to maintain through-hole reliability. DfR has extensive experience in both modeling the filled via concept and analyzing failures associated with this defect. For more information contact, Nathan Blattau, firstname.lastname@example.org.