DfR Solutions' Craig Hillman authors Package on Package Article

PoP packaging is quickly evolving into one of the next generation packaging technologies due to the increased need to miniaturize electronics. To get a flavor for the issues associated with the manufacturability of assemblies utilizing these packages, read DfR's recent article published in the SMT February 2012 issue. For more information, contact Craig Hillman.

DfR Solutions' Greg Caswell presents at Central Texas Electronics Association in Austin, TX: Feb 21

Greg Caswell will be making a presentation on "Challenges with Package on Package (PoP)" at this local chapter meeting of IMAPS/SMTA and IPC members. For more information contact Greg Caswell.

Central Texas Electronics Association

Electronics Design & Manufacturing Symposium 

Tuesday, February 21, 2012

Freescale Bldg A Conference Center at 7700 W. Parmer Lane

Program:

3:00 - Registration Begins

3:30 - Welcome and Introductions

3:35 - "Comparing Electronic Component Package Materials and Substrate Vendors for

Solder-Joint Reliability Improvements," Joah Rayos, Packaging Engineer, Freescale

4:05 - "Challenges With Package on Package (PoP) Technology"

Greg Caswell, Senior Member of Technical Staff, DfR Solutions

4:35 - Break & Networking

4:45 - "Next Generation Cyber Threats”

John Pirc, Senior Product Line Manager, HP-TippingPoint

5:15 - "Introduction to DSP with the ARM Cortex-M4 Microcontroller"

Sergio Liberman, Senior Microcontroller Systems Engineer, Freescale

5:45 - Closing Remarks

6:00 - Food & Refreshments Served and More Networking

Registration:

RSVP to Bob Baker at: rjbakeratx@austin.rr.com

There is no charge for SMTA and IMAPS members; $10 for all non-members

Event Location:

Freescale Semiconductor Bldg A Conference Center at 7700 West Parmer Lane, Austin, Texas

See Map at: (Map to Freescale)

Record Attendance at DfR's "Modeling and Simulation in Electronic Packaging" Course

A packed audience at the 2011 Electronic Packaging and Technologies Conference listened to Craig Hillman provide a comprehensive understanding on how to model and simulate the reliability of the latest semiconductor packaging technologies, including copper wire bonds, through silicon vias (TSV), package on package (PoP), and low glass transition temperature (Tg) underfill. For more information on how DfR is driving modeling and simulation (M&S) to the common engineer, please contact Nathan Blattau.

How to Choose a Reliable Package on Package (PoP)

One company's solution can be another company's nightmare, especially in component packaging. A desire to maximize functionality and fit space constraints can result in something like this monster (25mm x 50mm) package on package (PoP). While likely satisfying a market need, this component will be challenging from a manufacturability and reliability perspective. For example, the package weight will likely reduce solder ball height to less than half the diameter, increasing the likelihood of pad cratering and thermo-mechanical fatigue. If you are looking for real solutions to PoP challenges, contact Craig Hillman, chillman@dfrsolutions.com.

PoP Goes the...Package

The need for innovative packaging to maintain Moore's Law has become increasingly necessary and Package on Package (PoP) has become a popular solution. While there are numerous advantages to PoP, including higher densities and yields, few are aware of PoP's limitations. In our insightful white paper, DfR details some of the advantages and challenges of this wrinkle in 3D packaging. For more information, please contact Randy Kong, rkong@dfrsolutions.com.