IPC Designers Council AHOT Chapter meeting and Technical presentation June 12, 11:30 AM

Chapter Meeting, National Instruments, 11500 N Mopac Expressway, Bldg C, rm IS15, June 12, 2012, 11:30 A.M. (approx 1.5 hrs)

LUNCH MEETING RSVP required-See below instructions

1)    "Adopting a Flexible PCB Replication and Reuse Methodology"

2)    "Automating the Library Creation Process For Engineers and PCB
Designers for both Schematic logic symbols and PCB footprints"

Presented by Ron Smith

Brief BIO: Ron Smith (Smitty)

"Smitty" has been involved with Printed Circuit Boards for almost 40 years. First having worked for a company that manufactured Flexible Circuits. Manufacturing lead to an interest in circuit design and Smitty went to work for a design Service Bureau doing hand layouts and then using CAD. He started his own deign consulting business using PCAD and after 5 years went to work for PCAD as an Application Engineer. 10 years later and PCAD changing names to Cadam,  IBM, Altium, Accel, Protel and then Altium again he joined EMA Design Automation where he's been for 13 years. CID certified, his role has evolved from Application Engineer to Departmental Manager to Member of the Executive Team with the goal always being to provide engineers with software automation that addresses their design challenges.


1)   Adopting a Flexible PCB Replication and Reuse Methodology


Design Re-use IP has been utilized in IC and system on chip (SoC) designs effectively for many years. In PCB design, however, replication and re-use has seen slower adoption. This, in part, has been due to the rigid methodology of hierarchical blocks or symbols employed at the schematic requiring an identical PCB layout at the physical stage. These methods work in identically replicated circuits but often circuits are not 100% identicalnwithin and between designs. Circuits will frequently differ in componentn counts, net names, connectivity and PCB layer stack-up, breaking the traditional strict re-use methodology. This presentation will discuss experiences investigating and subsequently implementing a flexible replication and reuse methodology using Cadence Allegro PCB and CircuitSpace from Cadence Connection partner EMA Design Automation. We will explore the criteria used to evaluate potential options and how the current solution from Cadence and EMA was able to best meet customer's flexible replication and reuse requirements.

To get the most out of PCB design IP reuse a flexible solution is needed. Employing a flexible replication and re-use methodology can significantly reduce design and verification time especially for boards with repetitive circuitry like multi-channel designs or ATE boards Solutions from Cadence and their partners enable a highly effective flexible replication and reuse environment for Allegro PCB.

2)   Automating the Library Creation Process For Engineers and PCB Designers for both Schematic logic symbols and PCB footprints



CAD vendors have been lacking in creating effective and productive library development tools. Typically they employ 2 independent environments; 1 for logic symbols and another for PCB footprints with dissimilar editors. This proves to be unproductive with no immediate means of verifying the symbol with the footprint in the library development stage.

EDABuilder provides one unified user environment for the creation of logic symbols and PCB footprints with part verification through crossprobing capabilities. EDABuilder employs the most power PDF extraction of vendor datasheets. Content and data structures are extracted in minutes, versus days with a manual approach. Intelligent symbol partitioning allows a designer to use a higher level of abstraction to assign the symbol pins to graphical symbols. Other functions include an easy to use select and drop between pin tables and the symbol, assign and partition the pins to symbols, as well as the ability to move pins onto the symbols, between symbols, and back to the spreadsheet.

PCB footprint generation fully supports both the IPC-7351 standard and user defined requirements across a broad range of component families. The process, driven by rules, settings, and form entered component dimensioning, accurately builds parts in a consistent and repetitive process. Providing a single environment for PCB library generation avoids the common problem of mismatched symbol and footprint models. All too often, discrepancies between symbols and footprints are found in the middle of the design process leading to lost time and costly rework. This is a hard problem to solve since most design teams build their schematic and PCB libraries using separate tools making verification difficult. EDABuilder ensures that the symbol and footprint match from the start with its unified design environment, easy cross probing, and rigorous verification checks. This level of integration between the PDF data sheet, schematic symbol, and PCB footprint represents the next advancement in the library development process.

Pizza and drinks will be provided:   RSVP to
Linda at 512-259-2465,     or email    <mailto:linda@kutzsales.com>
linda@kutzsales.com